『3D IC』のカバーアート

3D IC

3D IC

著者： Siemens Digital Industries Software
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As the semiconductor industry struggles with the limits of Moore’s Law, traditional monolithic scaling is no longer enough to meet performance, power, area and cost demands in technology, design, analysis, and manufacturing. 3D IC by Siemens is your go-to podcast for exploring the cutting-edge world of 3D IC packaging—a revolutionary approach reshaping semiconductor design, system integration, and heterogeneous computing. Join industry leaders, engineers, and innovators as we break down advanced IC packaging solutions like 2.5D/3D IC, FCBGA, FOWLP, and more. Discover how chiplets, multi-die integration, and high-bandwidth memory (HBM) are driving higher performance, lower power consumption, and scalable architectures. In each episode, we dive deep into the challenges and opportunities of IC design and manufacturing, including: Roadmap for advanced packaging and heterogeneous integration in semiconductor scaling Mainstream adoption of 3D IC—key challenges and breakthroughs Optimizing micro-architecture and integration platforms for performance and efficiency Strategic planning of chiplets and interposers for hierarchical device integration Leveraging early predictive multi-physics analysis to enhance design accuracy Automating design and routing for RDL-based fan-out wafer-level packaging (FOWLP) Exploring glass substrates for superior electrical and thermal performance Developing test-vehicles and daisy chain designs for architectural validation Ensuring reliability and manufacturability in 3D IC heterogeneous integration Mastering Signal Integrity (SI) and Power Integrity (PI) Analysis for high-speed systems Managing thermal challenges in stacked die architectures Subscribe now and stay ahead in the world of 3D IC. Learn more: Siemens 3D IC Packaging SolutionsSiemens Digital Industries Software 政治・政府
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  • From Hype to Engineering: How AI Actually Works in 3D IC design

    From Hype to Engineering: How AI Actually Works in 3D IC design
    2026/08/05
    What can AI actually do in 3D IC design today — and what's still science fiction? What you’ll learn… (01:25) Sudarshan's role leading global 3D IC software R&D at Siemens (02:30) The real starting challenges of 3D IC design — and why there's no playbook yet (05:25) Breaking down organizational silos between silicon, packaging, and mechanical teams (05:49) Why semiconductor AI must be domain-specific, not just a chatbot (10:34) AI as an engineering co-pilot for design space exploration (13:38) Beyond design: AI's impact on materials, yield, and reliability prediction (17:41) The shift toward AI-native, multiphysics co-optimization workflows (21:16) Ethical pitfalls: explainability, data governance, and IP protection (24:50) AI's role in the global, geopolitical semiconductor landscape (27:48) How Siemens is building this with HEEDS and the Fuse EDA AI system More about this episode… In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Sudarshan Deo, Software Engineering Manager for 3D IC at Siemens, about what AI can — and can't — actually do in 3D IC design today, and why the hype rarely matches the reality on the ground. Sudarshan breaks down the biggest misconception in the field: that AI is either a magic box that will design chips end-to-end, or just hype dressed up as a buzzword. The truth, he argues, sits in between — semiconductor AI has to be domain-specific, physics-aware, and explainable, not a general-purpose chatbot. He walks through where AI is already delivering value, from narrowing design space exploration in chiplet partitioning and floor planning, to identifying promising materials and process combinations, to flagging reliability risks like thermal cycling and stress before they become expensive late-stage fixes. The conversation also covers the organizational side — how 3D IC forces silicon, packaging, and mechanical teams out of their silos — and the ethical considerations that come with deeper AI adoption: explainability, data governance, and IP protection across foundries. Sudarshan closes by outlining Siemens' own approach, using Simcenter HEEDS for design space exploration and the Fuse EDA AI system to orchestrate engineering workflows end to end, while making clear that none of this replaces human judgment — it just changes how fast and how far that judgment can reach. Ideal for: 3D IC and chiplet design engineers, EDA tool users, AI/ML practitioners in semiconductor workflows, packaging and reliability engineers, and anyone evaluating where AI genuinely helps versus where it's overhyped in chip design. Connect with Tova Levy LinkedIn Website Connect with Sudarshan Deo LinkedIn Siemens EDA
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    33 分
  • Nothing's for Free: Piyush Sancheti on the Real Trade-Offs Behind 3D IC Adoption

    Nothing's for Free: Piyush Sancheti on the Real Trade-Offs Behind 3D IC Adoption
    2026/08/12
    From AI accelerators to automotive silicon, what does it actually take — organizationally, economically, and technically — to make 3D IC work in the real world? What you’ll learn... (01:59) What's already shipping: real-world 2.5D and 3D IC products in data centers, mobile devices, and AI accelerators — and why linear, monolithic SoC flows no longer scale for 3D IC design (05:44) Is 3D IC the right economic decision? Weighing ROI and the two forks in the road (08:24) Geopolitics and the shift from single-foundry lock-in to a fragmented, multi-supplier ecosystem (11:01) The cultural shift: bringing electrical, mechanical, and materials science disciplines together (13:54) Why EDA is the glue for multidisciplinary 3D IC design (14:32) STCO explained: shifting design decisions left with a unified "cockpit" view (18:36) Inside the expanded Siemens–NVIDIA AI partnership announced at CES 2026 (20:03) Why system companies are moving into custom silicon — Meta's MTIA and Tesla's Dojo 3 (24:11) Looking ahead: integrated photonics, glass interposers, and wafer-scale computing (29:37) Physical AI at the edge: latency, power, and reliability requirements More about this episode... In this episode of the Siemens 3D IC Podcast, closing out the season, host Tova Levy speaks with Piyush Sancheti, VP of Central Engineering Solutions (3D IC) at Siemens EDA, for a full-circle look at where 3D IC adoption stands today. Piyush explains that 3D IC has moved well past research: 2.5D packaging is now mainstream in AI and HPC, and true 3D stacking is moving beyond HBM into logic dies. But the biggest lesson for early adopters isn't technical, it's organizational: linear, monolithic SoC flows don't scale once packaging, multi-physics, and manufacturing all have to be considered together from day one. That theme carries through the economics of adoption (there's no one-size-fits-all, it depends on end market), the geopolitical push toward a diversified, multi-supplier ecosystem, and the cultural shift needed to unite electrical, mechanical, and materials engineering teams. Piyush also unpacks STCO (system technology co-optimization) as a shift toward earlier design-space exploration, Siemens' unified "cockpit" vision for 3D systems, and the expanded Siemens–NVIDIA partnership announced at CES 2026. He closes by looking at why system companies like Meta (MTIA) and Tesla (Dojo 3) are building their own custom silicon, what's next for the industry (co-packaged optics, glass interposers, wafer-scale computing), and how physical AI at the edge is reshaping 3D IC's latency and power requirements. Ideal for: 3D IC architects, EDA users, chip and system-level design leaders, semiconductor strategists tracking geopolitical and supply-chain shifts, and anyone trying to understand where multi-die integration is headed next. Connect with Tova Levy LinkedIn Website Connect with Piyush Sancheti LinkedIn Siemens EDA
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    33 分
  • Beyond the Silo: Managing Data at the Speed of 3D IC Design

    Beyond the Silo: Managing Data at the Speed of 3D IC Design
    2026/07/29
    What happens when a single untracked design change turns into a multi-billion-dollar public scandal? What you’ll learn... (00:00) Why data — not just design — is the hidden challenge behind every 3D IC (01:55) A real-world case study: how poor traceability triggered a costly public recall (04:06) The "mini database" problem: how tool sprawl scatters chip design data (06:10) Why 3D IC makes data management so much harder than traditional SoC design (08:32) What is an "atomic change," and why it's critical for design consistency (10:15) Three foundational building blocks for managing data at scale (12:42) IPLM vs. PLM: what's the difference, and why do you need both? (15:19) The human cost of poor data management: hunting, silos, and burnout (18:15) Why better data management makes onboarding faster and easier (19:42) Inside the Perforce–Siemens partnership and what's next for 3D IC workflows More about this episode… In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Vishal Moondhra, VP of Solutions at Perforce Software, about why data — not just design complexity — may be the biggest hidden risk in 3D IC development, and what teams can do about it. Vishal opens with a real-world cautionary tale: a major chip company that shipped a security flaw across its product line, then discovered it lacked the traceability to know which variants needed the fix — a gap that led to a multi-billion-dollar hit to its market cap. From there, the conversation digs into why 3D IC makes this problem so much worse: every tool builds its own "mini database," changes ripple across interdependent dies and interposers, and AI-driven workflows are only multiplying the volume of data being generated. Vishal introduces the concept of the "atomic change" — capturing everything or nothing, so partial updates never slip through — and lays out the foundational building blocks of scalable data management, before drawing a clear line between PLM (product-level, slow-moving, heavily governed) and IPLM (design-level, fast-paced, daily). He closes by walking through the growing partnership between Perforce and Siemens, and how IPLM is being integrated across tools like Solido, Calibre, and Questa to give engineering teams a single source of truth. Ideal for: 3D IC and SoC design teams, data and IP management leads, verification and design engineers, EDA tool users, and anyone responsible for traceability, compliance, or onboarding across a fast-scaling chip design organization. Connect with Tova Levy LinkedIn Website Connect with Vishal Moondhra LinkedIn Perforce IPLM
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    23 分
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