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  • Breaking the coverage bottleneck: Unifying verification for modern chips

    Breaking the coverage bottleneck: Unifying verification for modern chips
    2026/04/02
    Harry Foster talks with Vladislav Palfy, Director of Solutions Management at Siemens EDA, about why coverage closure has become one of the biggest bottlenecks in modern verification. Drawing on insights from his white paper, Questa One Unified Coverage Solution: Transforming Verification Through Intelligence, Vladislav explains how traditional brute-force approaches to coverage are struggling to keep up with the complexity of today’s semiconductor designs. Learn how a unified, intelligent approach to coverage—combining planning, automation, and analytics—helps teams break through coverage plateaus, reduce regression effort, and achieve faster, more confident verification closure. Key Discussion Points Why coverage closure is so hard today: How increasing design complexity and fragmented workflows have turned the last 10% of coverage into a major project risk. The coverage plateau problem: Why adding more tests often stops improving coverage—and how intelligent analysis helps teams target the real gaps. Unified coverage explained: How integrating planning, analysis, and execution creates a more systematic and predictable path to verification completeness. The role of the unified coverage database: How a centralized coverage architecture enables collaboration across teams, tools, and geographies. From brute force to intelligent automation: How targeted test generation and coverage analytics dramatically reduce regression workloads. Looking ahead: How AI-driven verification and predictive coverage planning could transform how engineers approach coverage closure in the next generation of chip design.
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    19 分
  • SDC verification as a first-class asset: A deep dive with Chandu Challapalli

    SDC verification as a first-class asset: A deep dive with Chandu Challapalli
    2026/01/27
    In this episode of Bugged Out, Harry Foster talks with Chandu Challapalli, Senior Management Director at Siemens EDA, about why timing constraints must be treated as first-class verification assets. Drawing on insights from his white paper, A Guide to SDC-Based Timing-Intent Verification with Questa One, Chandu explains how automated SDC verification uncovers hidden timing risks, balances under- and over-constraining, and shifts timing validation earlier in the design cycle. Learn how Questa One brings structure and automation to timing-intent verification—helping teams achieve faster signoff and greater confidence in first-pass silicon success. Key Discussion Points Why Timing Constraints Matter: How SDC files capture design intent—and why ignoring their verification invites silicon risk. What Is Timing-Intent Verification?: A clear explanation of validating clocks, exceptions, and constraints against real design behavior. Finding the Right Balance: The hidden costs of under-constraining versus over-constraining timing. Common SDC Pitfalls: Missing clocks, invalid exceptions, and legacy constraints that mask real bugs. Shifting Left on Timing: Why verifying constraints early—alongside RTL—reduces late-stage surprises. What’s Next: A glimpse into continuous, AI-assisted timing-intent verification and tighter frontend/backend alignment.
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    14 分